The present invention relates to a semiconductor memory and, more particularly, to a technique which is effective when used in a dynamic random access memory (which will be hereinafter referred to as an "RAM") of a half precharge system, for example, for precharging a data line to a half level of the supply voltage.
A 1-bit memory cell of a dynamic RAM is composed of an information storing capacitor Cs and an address selecting insulated gate field effect transistor (which will be hereinafter referred to as a "MOSFET") Qm and stores information as logic "1" and "0" represented by the presence or absence of charges in the capacitor Cs. The read operation of the information is conducted by connecting the capacitor Cs with a common data line D while the MOSFET Qm is ON and by sensing how the potential of the data line D changes in accordance with the quantity of charges stored in the capacitor Cs. When the memory array is highly integrated to have a high capacity, a memory cell MC is miniaturized, and many memory cells are connected with the data line D. In this case, the ratio Cs/Co of the capacitor Cs to the stray capacity Co of the data line D takes a very small value. As a result, the potential change of the data line D due to the quantity of charges stored in the capacitor Cs takes a very minute value.
In order to generate a reference potential when such fine value is to be detected, the (half precharge) concept of precharging the data line in advance with a substantially half level of the supply voltage Vcc to use the half precharge level has already been developed by us (refer to our Japanese Patent Application No. 57-164831, for example).
However, our further studies have revealed that such precharge system using of Vcc/2 will raise the following problems. In the operation of selecting the word line, more specifically, a selected memory cell is coupled to one data line. Here, the address selecting MOSFET in the memory cell has an interelectrode capacitance, a gate capacitance or a MOS capacitance which cannot be considered a negligible coupling capacitance. As a result, if a selection signal is fed to the word line, the undesirable coupling between the word line through the MOS capacitance and one data line causes the undesirable potential fluctuations which are considered noise to be imparted to the one data line. The other data line is left at the precharge level. This degrades the margin of the fine level read from the aforementioned memory cell.